logicanalyzer/Electronics/LogicAnalyzer/LogicAnalyzer_JasonYANG170/KiCad 8/AnalyzerBoxPCB_fork.kicad_pcb

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	(general
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	(paper "A4")
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		(37 "F.SilkS" user "Top Silkscreen Layer")
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		(41 "Cmts.User" user "User.Comments")
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		(48 "B.Fab" user "Bottom Assembly Layer")
		(49 "F.Fab" user "Top Assembly Layer")
		(50 "User.1" user "Ratline Layer")
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		(52 "User.3" user "Component Marking Layer")
		(53 "User.4" user "3D Shell Outline Layer")
		(54 "User.5" user "3D Shell Top Layer")
		(55 "User.6" user "3D Shell Bottom Layer")
		(56 "User.7" user "Drill Drawing Layer")
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		(58 "User.9" user)
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	(net 22 "CHAN_22")
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	(net 24 "CHAN_20")
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